1. Field of the Invention
The present invention generally relates to the field of fabrication of integrated circuits, and, more particularly, to the formation of metal layers over a patterned dielectric, such as trenches and visa, by a wet chemical deposition process, such as electroless plating.
2. Description of the Related Art
In an integrated circuit, a huge number of circuit elements, such as transistors, capacitors, resistors, and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of the integrated circuits, generally the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing for the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as visa, wherein the metal lines and visa may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the package density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide for the desired circuit functionality. Therefore, the number of stacked metallization layers may increase as the number of circuit elements per chip area becomes larger. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of up to twelve stacked metallization layers that are required, for example, for sophisticated aluminum-based microprocessors, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections. For example, copper is a metal generally considered to be a viable candidate for replacing aluminum due to its superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures due to copper's characteristics to form non-volatile reaction products. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used, wherein a dielectric layer is first applied and then patterned to define trenches and visa, which are subsequently filled with copper. A further major drawback of copper is its propensity to readily diffuse in silicon dioxide and other dielectric materials.
It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may then readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. Since the dimensions of the trenches and visa currently approach a width or a diameter of approximately 0.1 μm and even less with an aspect ratio of the visa of about 5 or more, the deposition of a barrier layer reliably on all surfaces of the visa and trenches and subsequent filling thereof with copper substantially without voids is one of the most challenging issues in the fabrication of modem integrated circuits.
Currently, the formation of a copper-based metallization layer is performed by patterning an appropriate dielectric layer and depositing the barrier layer, for example comprised of tantalum and/or tantalum nitride, by advanced PVD techniques, such as sputter deposition. For the deposition of a barrier layer of 10 to 50 nm in visa having an aspect ratio of 5 or even more, enhanced sputter tools are usually employed. Such tools offer the possibility to ionize a desired fraction of the target atoms after sputtering them off the target, thereby enabling to a certain degree the control of the bottom coverage and the sidewall coverage in the visa. Thereafter, the copper is filled in the visa and trenches, wherein electroplating has proven to be a viable process technique, since it is capable of filling the visa and trenches with a high deposition rate, compared to CVD and PVD rates, in a so-called bottom-up regime, in which the openings are filled starting at the bottom in a substantially void-free manner. Generally, in electroplating a metal, an external electric field has to be applied between the surface to be plated and the plating solution. Since a substrate for semi-conductor production may be contacted at restricted areas, usually at the perimeter of the substrate, a conductive layer covering the substrate and the surfaces that are to receive a metal has to be provided. Although the barrier layer previously deposited over the patterned dielectric may act as a current distribution layer, it turns out, however, that in view of crystallinity, uniformity and adhesion characteristics, presently, a so-called copper seed layer is required in the subsequent electroplating process to obtain copper trenches and visa having the required electrical and mechanical properties. The copper seed layer is typically applied by sputter deposition using substantially the same process tools as are employed for the deposition of the barrier layer.
For dimensions of 0.1 μm and less of visa in future device generations, the sputter deposition of extremely thin metal layers having a high degree of conformity as required for the barrier layer and the seed layer may become a limiting factor, since the coverage characteristics of the above-described advanced sputter tools may not be further enhanced without significant modifications of these tools, which seems to be not a straightforward development. Especially the deposition of the seed layer may not be performed in a straightforward manner by PVD as here the uniformity of the seed layer—contrary to the barrier layer “only” requiring a sufficient and complete coverage of the inner surfaces of the openings—determines to a certain degree the uniformity of the following electroplating process. Moreover, PVD techniques producing extremely thin layers appropriate for barrier layers may result, when applied to the formation of seed layers, in an increased electric resistance, thereby reducing an initial deposition rate of the subsequent electroplating process.
In the printed wire board industry, an electroless copper deposition is frequently used for forming copper layers on generally non-conductive patterned structures. The electroless deposition requires an active initiation of a chemical reaction of the agents contained in the plating solution to reduce copper and deposit a copper layer on the structure. The initiation may be accomplished by a catalytic material or, as presently used in printed wire boards, by plating solutions including colloids. Although plating solutions containing colloids may successfully be applied for coating print boards with visa of several tens μm, this deposition method is quite inappropriate for metallization layers of sophisticated integrated circuits for the following reasons. The colloidal plating solutions may readily develop clusters having a size that may considerably exceed the size of the circuit features of interest. Moreover, the adhesion properties of the plated copper do not conform with the requirements of the semiconductor industry, since usually the excess copper is removed by chemical mechanical polishing demanding a high mechanical stability and thus adhesion of the copper to the adjacent material(s). Consequently, the formation of clusters, even if the size thereof may be maintained below a critical level, in combination with a reduced adhesion, may entail an increased electromigration effect of the copper lines and visa, thereby rendering a corresponding approach less than desirable.
In view of the above-explained situation, it is therefore desirable to provide a technique enabling the efficient formation of a metal layer, such as a copper and/or a copper alloy layer, by electroless deposition, thereby avoiding or at least reducing one or more of the above-identified problems.